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📘 Half Adder - Notes

🔹 Definition

A Half Adder is a basic combinational logic circuit that performs the addition of two binary digits. It has two inputs — A and B — and produces two outputs: Sum (S) and Carry (C).

🔹 Binary Addition Process

The rules for binary addition of single bits are:

🔹 Truth Table

ABSum (S)Carry (C)Justification
00000 + 0 = 0
01100 + 1 = 1
10101 + 0 = 1
11011 + 1 = 10

🔹 Sum and Carry Expressions (SOP)

From the truth table:

Hence:

🔹 Half Adder Implementation Using XOR and AND

This is the basic and most common implementation using standard logic gates:

Half Adder using XOR and AND gates

🔹 Half Adder Implementation Using NAND Gates Only

Using only NAND gates, we can derive the same logic:

Half Adder using NAND gates only

🔹 Half Adder Implementation Using NOR Gates Only

Similarly, the Half Adder can be built using only NOR gates:

Half Adder using NOR gates only

🧠 Multiple Choice Questions – Half Adder

Q1. What are the two outputs of a Half Adder?




Q2. What is the symbolic Boolean expression for the Sum output of a Half Adder?




Q3. What is the Carry output when A = 1 and B = 1?




Q4. The Half Adder circuit cannot:




Q5. Which gate alone can be used to implement a Half Adder?




Q6. What is the Carry expression in SOP form?




Q7. If A = 0 and B = 1, what is the Sum output?




Q8. The gate used for generating the Carry output is:




Q9. Which combination correctly represents a Half Adder using basic gates?




Q10. What is the Sum output when both A and B are 1?




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